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ISL28276, ISL28476
Data Sheet April 20, 2007 FN6301.1
Dual and Quad Precision Micropower Single Supply Rail-to-Rail Input and Output Precision Op Amps
The ISL28276 and ISL28476 are Dual and Quad channel micropower precision operational amplifier optimized for single supply operation at 5V and can operate down to 2.4V. For equivalent performance in a single channel op-amp reference EL8176. The ISL28276 and ISL28476 feature an Input Range Enhancement Circuit (IREC) which enables both parts to maintain CMRR performance for input voltages equal to the positive and negative supply rails. The input signal is capable of swinging 0.5V above a 5.0V supply (0.25V for a 2.4V supply) and to within 10mV from ground. The output operation is rail to rail. The both parts draw minimal supply current while meeting excellent DC-accuracy, AC-performance, noise and output drive specifications. Offset current, voltage and current noise, slew rate, and gain-bandwidth product are all two to ten times better than other micropower op-amps with equivalent supply current ratings. The ISL28276 and ISL28476 can be operated from one lithium cell or two Ni-Cd batteries. The input range includes both positive and negative rail.
Features
* 60A supply current per channel * 100V max offset voltage * 500pA input bias current * 400kHz gain-bandwidth product * 115dB PSRR and CMRR * Single supply operation down to 2.4V * Input is capable of swinging above V+ and within 10mV of Ground * Rail-to-rail output * Output sources 31mA load current * Pb-free plus anneal available (RoHS compliant)
Applications
* Battery- or solar-powered systems * 4mA to 25mA current loops * Handheld consumer products * Medical devices * Thermocouple amplifiers * Photodiode pre-amps * pH probe amplifiers
Ordering Information
PART NUMBER (Note) ISL28276IAZ ISL28276IAZ-T7 Coming Soon ISL28476FAZ PART TAPE & MARKING REEL 28276 IAZ 28276 IAZ PACKAGE (Pb-Free) PKG. DWG. #
97/Tube 16 Ld QSOP MDP0040 7" 16 Ld QSOP MDP0040 (1k pcs)
28476 FAZ 97/Tube 16 Ld QSOP MDP0040
Coming Soon 28476 FAZ 7" 16 Ld QSOP MDP0040 ISL28476FAZ-T7 (1k pcs) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL28276, ISL28476 Pinouts
ISL28276 (16 LD QSOP) TOP VIEW
NC 1 NC 2 OUT_A 3 + IN-_A 4 IN+_A 5 EN_A 6 V- 7 NC 8 + 16 NC 15 V+ 14 OUT_B 13 IN-_B 12 IN+_B 11 EN_B 10 NC 9 NC OUT_A 1 IN-_A 2 + IN+_A 3 V+ 4 IN+_B 5 IN-_B 6 OUT_B 7 NC 8 + + +
ISL28476 (16 LD QSOP) TOP VIEW
16 OUT_D 15 IN-_D 14 IN+_D 13 V12 IN+_C 11 IN-_C 10 OUT_C 9 NC
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FN6301.1 April 20, 2007
ISL28276, ISL28476
Absolute Maximum Ratings (TA = +25C)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V, 1V/s Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V ESD tolerance, Human Body Model . . . . . . . . . . . . . . . . . . . . . .3kV ESD tolerance, Machine Model . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Information
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite Ambient Operating Temperature Range . . . . . . . . .-40C to +125C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Operating Junction
Electrical Specifications
PARAMETER VOS V OS -----------------Time V OS --------------T IOS IB eN
V+ = 5V, 0V, VCM = 0.1V, VO = 1.4V, TA = +25C unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +125C CONDITIONS MIN -100 -150 TYP 20 1.2 0.3 0.25 -2 -2.5 f = 0.1Hz to 10Hz fO = 1kHz fO = 1kHz Guaranteed by CMRR test VCM = 0V to 5V V+ = 2.4V to 5V VO = 0.5V to 4.5V, RL = 100k VO = 0.5V to 4.5V, RL = 1k 0 90 80 90 80 350 350 115 115 550 25 3 130 4.990 4.97 4.800 4.750 0.13 0.10 0.10 0.09 4.996 4.880 0.17 0.13 400 0.20 0.25 0.17 0.19 6 30 175 225 0.5 1 25 0.1 5 1.3 2.0 2 2.5 MAX 100 150 UNIT V V/Mo V/C nA nA VP-P nV/Hz pA/Hz V dB dB V/mV V/mV mV mV V V V/s V/s kHz
DESCRIPTION Input Offset Voltage Long Term Input Offset Voltage Stability Input Offset Drift vs Temperature Input Offset Current Input Bias Current Input Noise Voltage Peak-to-Peak Input Noise Voltage Density
iN CMIR CMRR PSRR AVOL
Input Noise Current Density Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain
VOUT
Maximum Output Voltage Swing
Output low, RL = 100k Output low, RL = 1k Output high, RL = 100k Output high, RL = 1k
SR+ SRGBW
Positive Slew Rate Negative Slew Rate Gain Bandwidth Product
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FN6301.1 April 20, 2007
ISL28276, ISL28476
Electrical Specifications
PARAMETER IS,ON IS,OFF IS,ON IS,OFF ISC+ ISCVS VINH VINL IENH IENL V+ = 5V, 0V, VCM = 0.1V, VO = 1.4V, TA = +25C unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +125C (Continued) CONDITIONS ISL28276 all channels enabled. MIN TYP 120 4 ISL28476 all channels enabled. 240 8 RL = 10 RL = 10 29 23 24 19 2.4 2 0.8 VEN = 5V VEN = 0V -0.1 0.7 0 1.3 1.5 +0.1 31 26 MAX 156 175 7 9 312 350 14 18 UNIT A A A A mA mA V V V A A
DESCRIPTION Supply Current, Enabled Supply Current, Disabled Supply Current, Enabled Supply Current, Disabled Short Circuit Sourcing Capability Short Circuit Sinking Capability Minimum Supply Voltage Enable Pin High Level Enable Pin Low Level Enable Pin Input Current Enable Pin Input Current
Typical Performance Curves
8 45 40 4 VS = 1.25V GAIN (dB) 0 AV = 1 -4 RL = 10k CL = 2.7pF RF = 100 RG = OPEN -8 100 1k VS = 2.5V VS = 1.0V GAIN (dB) 35 30 25 20 AV = 100 15 RL = 10k CL = 2.7pF 10 R /R = 99.02 FG RF = 221k 5 RG = 2.23k 0 100 1k VS = 1.25V VS = 1.0V VS = 2.5V
10k
100k
1M
10M
10k FREQUENCY (Hz)
100k
1M
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
FIGURE 2. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
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FN6301.1 April 20, 2007
ISL28276, ISL28476 Typical Performance Curves
200 INPUT OFFSET VOLTAGE (V) INPUT OFFSET VOLTAGE (V) VCM = VDD/2 150 AV = -1 100 50 0 -50 -100 -150 -200 0 1 2 3 4 5 OUTPUT VOLTAGE (V) VDD = 2.5V VDD = 5V
(Continued)
0
-20
VOS, V
-40
-60
-80
-100 0 1 2 3 4 5 COMMON-MODE INPUT VOLTAGE (V)
FIGURE 3. INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE
FIGURE 4. INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE
120 80 GAIN (dB) 40 0 -40 -80 1 10 100 1k 10k 100k 1M FREQUENCY (Hz)
80 40 PHASE () 0 -40 -80 -120 10M GAIN (dB)
100 80 PHASE 60 40
200 150 100 50 0 PHASE ()
20 0 -20 10
GAIN
-50 -100 -150 1M
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 5. AVOL vs FREQUENCY @ 100k LOAD
FIGURE 6. AVOL vs FREQUENCY @ 1k LOAD
120 110 100 90 PSRR (dB) 80 70 60 50 40 30 20 10 0 10 PSRR VS = 5VDC VSOURCE = 1VP-P RL = 100k AV = +1 100 1k 10k 100k 1M PSRR + CMRR (dB)
90 80 70 60 50 40 30 10 VS = 5VDC VSOURCE = 1VP-P RL = 100k AV = +1
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 7. PSRR vs FREQUENCY
FIGURE 8. CMRR vs FREQUENCY
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FN6301.1 April 20, 2007
ISL28276, ISL28476 Typical Performance Curves
2.56 2.54 2.52 VOUT 2.50 2.48 2.46 2.44 2.42 0 2 4 6 8 10 12 14 16 18 20 0 100 200 300 400 500 VS = 5VDC VOUT = 0.1VP-P RL = 500 AV = +1 VIN VIN VS = 5VDC VOUT = 0.1VP-P RL = 500 AV = -2
(Continued)
VOUT
FIGURE 9. SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 10. LARGE SIGNAL TRANSIENT RESPONSE
10.00 CURRENT NOISE (pA/Hz) VOLTAGE NOISE (nV/Hz)
1k
1.00
100
0.10
10
0.01 1 10 100 1k 10k 100k FREQUENCY (Hz)
1 10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 11. CURRENT NOISE vs FREQUENCY
FIGURE 12. VOLTAGE NOISE vs FREQUENCY
6 VOLTAGE NOISE (200nV/DIV) VIN 5 4
100K
VS +
V+ = 5V
VOLTS (V)
100K
3 2 1 0
Function Generator 33140A
DUT +
VS -
1K
VOUT
1VP-P
0
50
100 TIME (ms)
150
200
TIME (1s/DIV)
FIGURE 13. 0.1Hz TO 10Hz INPUT VOLTAGE NOISE
FIGURE 14. INPUT VOLTAGE SWING ABOVE THE V+ SUPPLY
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FN6301.1 April 20, 2007
ISL28276, ISL28476 Typical Performance Curves
INPUT BIAS, OFFSET CURRENTS (pA) 10k
(Continued)
155 135 115 95 75 55 35 2.0
1k
IB+
100
IOS
IB-
10
1 0 1 2 3 4 5 COMMON-MODE INPUT VOLTAGE (V)
SUPPLY CURRENT (A)
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
FIGURE 15. INPUT BIAS + OFFSET CURRENTS vs COMMON-MODE INPUT VOLTAGE
FIGURE 16. SUPPLY CURRENT vs SUPPLY VOLTAGE
120 n=7 110 CURRENT (A) CURRENT (A)
150 n=6 140 130 120 110 100 90 -40
100
90
80
70 -40
-20
0
20
40
60
80
100
120
-20
0
TEMPERATURE (C)
20 40 60 80 TEMPERATURE (C)
100
120
FIGURE 17. SUPPLY CURRENT vs TEMPERATURE VS = 1.2V ENABLED. RL = INF
FIGURE 18. SUPPLY CURRENT vs TEMPERATURE VS = 2.5V ENABLED. RL = INF
1200 n=7 1000 CURRENT (pA) 800 600 400 200 0 -40 CURRENT (pA)
1400 1200 1000 800 600 400 200 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 0 -40
n=7
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
FIGURE 19. IBIAS+ vs TEMPERATURE VS = 2.5V
FIGURE 20. IBIAS+ vs TEMPERATURE VS = 1.2V
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FN6301.1 April 20, 2007
ISL28276, ISL28476 Typical Performance Curves
1400 1200 CURRENT (pA) CURRENT (pA) 1000 800 600 400 200 0 -40 -20 0 20 40 60 80 100 120 n=7
(Continued)
1700 1500 1300 1100 900 700 500 300 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120
n=7
TEMPERATURE (C)
FIGURE 21. IBIAS- vs TEMPERATURE VS = 2.5V
FIGURE 22. IBIAS- vs TEMPERATURE VS = 1.2V
1200 n=7 1000 CURRENT (pA) 800 600 400 200 0 -40 CURRENT (pA)
1300 1100 900 700 500 300 100 -20 0 20 40 60 80 100 120
n=7
-100 -40
-20
0
TEMPERATURE (C)
20 40 60 80 TEMPERATURE (C)
100
120
FIGURE 23. INPUT OFFSET CURRENT vs TEMPERATURE VS = 2.5V
FIGURE 24. INPUT OFFSET CURRENT vs TEMPERATURE VS = 1.2V
200 150 100 VOS (V) 50 0 -50 -100 -150 -40
n=5
200 150 100 VOS (V) 50 0 -50 -100 -150
n=6
-20
0
20
40
60
80
100
120
-200 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 25. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = 2.5V
FIGURE 26. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = 1.2V
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FN6301.1 April 20, 2007
ISL28276, ISL28476 Typical Performance Curves
130 n=7
(Continued)
114 112 n=6
120 CMRR (dB) PSRR (dB) 110 108 106 100 104 90 -40 102 -40
110
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 27. CMRR vs TEMPERATURE VCM = +2.5V TO -2.5V
FIGURE 28. PSRR vs TEMPERATURE VS = 1.2V TO 2.5V
2.40 2.39 2.38 VOUT (V) 2.37 2.36 2.35 2.34 -40
n=5
-2.32 -2.33 -2.34 VOUT (V) -2.35 -2.36 -2.37 -2.38 -2.39
n=5
OU
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
-2.4 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
FIGURE 29. POSITIVE VOUT vs TEMPERATURE RL = 1k VS = 2.5V
FIGURE 30. NEGATIVE VOUT vs TEMPERATURE RL = 1k VS = 2.5V
2.4992 2.499 2.4988 2.4986 VOUT (V) 2.4984 2.4982 2.498 2.4978 2.4976 2.4974 -40
n=7
-2.4956 -2.4958 -2.496 -2.4962 VOUT (V) -2.4964 -2.4966 -2.4968 -2.497
n=7
-20
0
20
40
60
80
100
120
-2.4972 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 31. POSITIVE VOUT vs TEMPERATURE RL = 100k VS = 2.5V
FIGURE 32. NEGATIVE VOUT vs TEMPERATURE RL = 100k VS = 2.5V
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FN6301.1 April 20, 2007
ISL28276, ISL28476 Typical Performance Curves
14 12 10 8 6 4 2 0 -2 -4 -40 -20 0 20 40 60 80 100 120 0.5 -40 -20 0 20 40 60 80 100 120 0.6 IIH (A) IIL (nA) 0.7 0.8 n=7
(Continued)
0.9
n=5
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 33. IIL (EN) vs TEMPERATURE VS = 2.5V
FIGURE 34. IIH (EN) vs TEMPERATURE VS = 2.5V
0.18 n=5 0.16 SLEW RATE (V/s) SLEW RATE (V/s)
0.16 0.15 0.14 0.13 0.12 0.11 0.1 -40
n=7
0.14
0.12
0.1
0.08 -40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 35. + SLEW RATE vs TEMPERATURE VS = 2.5V INPUT = 0.75V AV = 2
FIGURE 36. - SLEW RATE vs TEMPERATURE VS = 2.5V INPUT = 0.75V AV = 2
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.4 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.2 1 0.8 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) 893mW
QS OP JA 16 =1 12 C /W
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.2 1 0.8 633mW 0.6
J QS O
A =1
P1
0.4 0.2 0 0 25
58
6
C
/W
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 37. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 38. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN6301.1 April 20, 2007
ISL28276, ISL28476 Pin Descriptions
ISL28276 (16 LD QSOP) 3 4 5 15 12 13 14 1, 2, 8, 9, 10, 16 ISL28476 (16 LD QSOP) 1 2 3 4 5 6 7 8, 9 10 11 12 7 13 14 15 16 6 11 PIN NAME OUT_A IN-_A IN+_A V+ IN+_B IN-_B OUT_B NC OUT_C IN-_C IN+_C VIN+_D IN-_D OUT_D EN_A EN_B Circuit 3 Circuit 1 Circuit 1 Circuit 4 Circuit 1 Circuit 1 Circuit 3 Circuit 2 Circuit 2 EQUIVALENT CIRCUIT Circuit 3 Circuit 1 Circuit 1 Circuit 4 Circuit 1 Circuit 1 Circuit 3 Amplifier A output Amplifier A inverting input Amplifier A non-inverting input Positive power supply Amplifier B non-inverting input Amplifier B inverting input Amplifier B output No internal connection Amplifier C output Amplifier C inverting input Amplifier B non-inverting input Negative power supply Amplifier D non-inverting input Amplifier D inverting input Amplifier D output Amplifier A enable pin internal pull-down; Logic "1" selects the disabled state; Logic "0" selects the enabled state. Amplifier B enable pin with internal pull-down; Logic "1" selects the disabled state; Logic "0" selects the enabled state.
V+ V+ LOGIC PIN VCIRCUIT 2 CIRCUIT 3 OUT VVCIRCUIT 4 V+
CAPACITIVELY COUPLED ESD CLAMP
DESCRIPTION
V+ IN-
IN+ V-
CIRCUIT 1
Applications Information
Introduction
The ISL28276 and ISL28476 are Dual and Quad channel CMOS rail-to-rail input, output (RRIO) micropower precision operational amplifier with an enable feature. The parts are designed to operate from single supply (2.4V to 5.0V) or dual supply (1.2V to 2.5V) while drawing only 120A of supply current. The device has an input common mode range that extends 10% above the positive rail and up to 100mV below the negative supply rail. The output operation can swing within about 4mV of the supply rails with a 100k load (reference Figures 29 through 32). This combination of low power and precision performance makes them suitable for solar and battery power applications.
the positive supply without introducing additional offset errors or degrading performance associated with a conventional rail-to-rail input operational amplifier. Many rail-to-rail input stages use two differential input pairs, a longtail PNP (or PFET) and an NPN (or NFET). Severe penalties have to be paid for this circuit topology. As the input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other causing drastic changes in input offset voltage and an undesired change in magnitude and polarity of input offset current. The ISL28276 and ISL28476 achieve input rail-to-rail operation without sacrificing important precision specifications and degrading distortion performance. The devices' input offset voltage exhibits a smooth behavior throughout the entire common-mode input range. The input bias current versus the common-mode voltage range gives us an undistorted behavior from typically 100mV below the
Rail-to-Rail Input
The input common-mode voltage range of the ISL28276 and ISL28476 is from the negative supply to 10% greater than
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FN6301.1 April 20, 2007
ISL28276, ISL28476
negative rail and 10% higher than the V+ rail (0.5V higher than V+ when V+ equals 5V). components can be mounted to the PC board using Teflon standoff insulators.
HIGH IMPEDANCE INPUT IN V+
Input Protection
All input terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. They have additional back-to-back diodes across the input terminals. For applications where the input differential voltage is expected to exceed 0.5V, external series resistors must be used to ensure the input currents never exceed 5mA.
Input Bias Current Compensation
The input bias currents are decimated down to a typical of 500pA while maintaining an excellent bandwidth for a micropower operational amplifier. Inside the ISL28276 and ISL28476 is an input bias canceling circuit. The input stage transistors are still biased with an adequate current for speed but the canceling circuit sinks most of the base current, leaving a small fraction as input bias current.
FIGURE 39. GUARD RING EXAMPLE FOR UNITY GAIN AMPLIFIER
Example Application
Thermocouples are the most popular temperature-sensing device because of their low cost, interchangeability, and ability to measure a wide range of temperatures. The ISL28276 (Figure 40) is used to convert the differential thermocouple voltage into single-ended signal with 10X gain. The ISL28276's rail-to-rail input characteristic allows the thermocouple to be biased at ground and the converter to run from a single 5V supply.
R4 100k R3 R2 K TYPE THERMOCOUPLE 10k 10k V+ + ISL28276 V-
Rail-to-Rail Output
A pair of complementary MOSFET devices are used to achieve the rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction. The PMOS sources current to swing the output in the positive direction. The output with a 100k load will swing to within 3mV of the supply rails.
410V/C + 5V
Enable/Disable Feature
The ISL28276 offers an EN pin that disables the device when pulled up to at least 2.2V. In the disabled state (output in a high impedance state), the part consumes typically 4A. By disabling the part, multiple ISL28276 parts can be connected together as a MUX. The outputs are tied together in parallel and a channel can be selected by the EN pin. The EN pin also has an internal pull down. If left open, the EN pin will pull to the negative rail and the device will be enabled by default.
R1 100k
FIGURE 40. THERMOCOUPLE AMPLIFIER
Proper Layout Maximizes Performance
To achieve the maximum performance of the high input impedance and low offset voltage, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. When input leakage current is a concern, the use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 39 shows a guard ring example for a unity gain amplifier that uses the low impedance amplifier output at the same voltage as the high impedance input to eliminate surface leakage. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. For further reduction of leakage currents,
12
FN6301.1 April 20, 2007
ISL28276, ISL28476 Quarter Size Outline Plastic Packages Family (QSOP)
A D N (N/2)+1
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
PIN #1 I.D. MARK
A A1 A2 b
0.068 0.006 0.056 0.010 0.008 0.193 0.236 0.154 0.025 0.025 0.041 16
0.068 0.006 0.056 0.010 0.008 0.341 0.236 0.154 0.025 0.025 0.041 24
0.068 0.006 0.056 0.010 0.008 0.390 0.236 0.154 0.025 0.025 0.041 28
Max. 0.002 0.004 0.002 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference
1, 3 2, 3 Rev. F 2/07
E
E1
1 B 0.010 CAB
(N/2)
c D E
e C SEATING PLANE 0.004 C 0.007 CAB b
H
E1 e L L1 N
L1 A c SEE DETAIL "X"
NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010 A2 GAUGE PLANE L 44 DETAIL X
A1
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN6301.1 April 20, 2007

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